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ADE7953
LAYOUT GUIDELINES
Figure 78 presents a basic schematic of the ADE7953 together
with its surrounding circuitry, decoupling capacitors at pins
VDD, VINTA, VINTD, and REF, and the 3.58 MHz crystal and
its load capacitors. The rest of the pins are dependent on the
particular application and are not shown here.
Figure 77 presents a proposed layout of a printed circuit board
(PCB) with two layers that have the components placed only on
the top of the board. Following these layout guidelines will help
in creating a low noise design with higher immunity to EMC
influences.
The VDD, VINTA, VINTD, and REF pins each have two
decoupling capacitors, one of μF order and a ceramic one of
220 nF or 100 nF. These ceramic capacitors need to be placed
closest to the ADE7953 as they decouple high frequency noises,
while the μF ones need to be place in close proximity.
The exposed pad of the ADE7953 is soldered to an equivalent
pad on the PCB. The AGND, DGND, and PULL_LOW pins
traces of the ADE7953 are then routed directly in to the PCB
pad.
The bottom layer is composed mainly of a ground plane
surrounding as much as possible the through hole crystal pins.
C6
0.1μF
Data Sheet
Figure 77. ADE7953 Top Layer Printed Circuit Board
C5
10μF
C3
7
8
17
0.1μF
2
RESET
ZX 1
C4
4.7μF
5
6
IAP
IAN
VINTD 3
C1
9
IBP
VINTA 15
0.1μF
Y1
3.58MHz
C7
20pF
C8
20pF
10
11
12
18
IBN
VN
VP
CLKIN
U1
ADE7953
CLKOUT 19
IRQ 22
ZX_I 21
C2
4.7μF
25
27
28
SCLK
MOSI/SCL/Rx
CS
REVP 20
CF1 23
CF2 24
C9
0.1μF
13
REF
MISO/SDA/Tx 26
C10
4.7μF
4
16
14
Figure 78. ADE7953 Crystal and Capacitors Connections
Rev. B | Page 68 of 72
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